The present invention relates to the art of electronic packaging, and more specifically to assemblies incorporating microelectronic components and to methods of making such assemblies.
Modem electronic devices utilize microelectronic components, commonly referred to as "integrated circuits" which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements. Such substrates may be secured to an external circuit board or chassis. Alternatively, in a so-called "hybrid circuit" one or more chips are mounted directly to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with a reliable electrical interconnection to the substrate. The interconnection between the chip itself and the supporting substrate is commonly referred to as "first level" assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as "second level" interconnection.
The first level interconnection structures connecting a chip to a substrate ordinarily are subject to a substantial stress caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperature of the chip and the substrate rises each time the device is turned on and falls each time the device is turned off. As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion, the chip and the substrate ordinarily expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and the substrate changes. This relative movement deforms the electrical interconnection between the chip and the substrate and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause breakage of the electrical interconnections. Thermal cycling stresses may occur even when the chip and substrate are formed from like materials having similar coefficients of thermal expansion, because the temperature of the chip may increase more rapidly than the temperature of the substrate when power is first applied to the chip.
Flip-chip bonding provides a method for interconnection. In flip-chip bonding, contacts on the surface of the chip are provided with bumps of solder. The substrate has contact pads arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces towards the top surface of the substrate, with each contact and solder bump on the chip being positioned on the appropriate contact pad of the substrate. The assembly is then heated so as to liquefy the solder and bond each contact on the chip to the confronting contact pad of the substrate. Because the flip-chip arrangement does not require leads arranged in a fan-out pattern, it provides a compact assembly. The area of the substrate occupied by the contact pads is approximately the same size as the chip itself. Moreover, the flip-chip bonding approach is not limited to contacts on the periphery of the chip. Rather, the contacts on the chip may be arranged in a so-called "area array" covering substantially the entire front face of the chip. Flip-chip bonding therefore is well-suited to use with chips having a large number of I/O contacts.
Early flip-chip connections, as shown in U.S. Pat. No. 3,303,393, incorporated copper core solder balls, each including a sphere of copper coated with a solder. One such solder ball was provided between each contact on the chip and each contact pad on the substrate. These connections worked well for small devices. With larger devices having greater differential thermal expansion, the rigid connections provided by the solid core solder balls tended to crack. Warpage or distortion of the chip or substrate made it difficult to engage all of the solid core solder balls between the chip and substrate simultaneously, or to engage all of the solid core solder balls between the chip and a test fixture.
Other flip-chip bonding techniques, commonly referred to as "controlled collapse chip connection" or "C4" bonding, utilized masses of relatively soft, high-lead solder, typically containing between 90 and 97 percent lead. The high lead solder forms a somewhat less rigid connection than the solid core solder balls, Deformation of the solder connection relieves the stresses caused by differential thermal expansion to some degree. However, assemblies made by flip-chip bonding with the C4 process are still susceptible to thermal stresses. The degree of flexibility provided by the high-lead solder connections is limited. The solder joints and may be subject to very high stress upon differential expansion of the chip and substrate. These difficulties are particularly pronounced with relatively large chips. An article entitled "Flip Chip Solder Bump (FCSB) Technology: An Example" by Karl J. Puttlitz, Sr., describes these problems. Moreover, it is difficult to test and operate or "burn-in" chips having an area array of contacts before attaching the chip to the substrate. Where the chips are provided with high-lead solder balls suitable for the C4 process and then clamped to a socket to engage the solder balls with test contacts, the solder creeps and deforms rapidly. It is also difficult to rework a chip bonded using the C4 process. Parts of the solder masses are removed from the contacts if the chip is separated from the substrate, leaving non-uniform partial solder masses on the chip contacts.
Commonly assigned U.S. Pat. Nos. 5,148,266 and 5,148,265, the disclosures of which are hereby incorporated by reference herein, provide substantial solutions to the problem of thermal stresses. Nonetheless, still further improvements would be desirable.